In semiconductor industries, packaging technology has been advanced for increasing reliability in packaging and mounting small-sized integrated semiconductor chips. For example, demands for miniaturization have accelerated the development of small packages having sizes close to the sizes of integrated semiconductor chips, and demands for reliable mounting technology have spurred the development of packaging technology for efficiently packaging semiconductor chips and improving mechanical and electrical characteristics of the packaged semiconductor chips.
In addition, various technologies have been developed to provide high-capacity semiconductor products and satisfy the demands for small-sized, high-performance electric/electronic products. For example, high-capacity semiconductor products can be fabricated using highly integrated memory chips (i.e., high-capacity memory chips). Highly integrated memory chips can be fabricated by integrating a larger number of cells into a given region of the memory chip.
However, it is difficult and takes a large amount of time to develop highly integrated memory chips. For example, it is necessary to develop fine pattern forming technology for highly integrated memory chips. However, it is difficult and takes a large amount of time to develop the fine pattern forming technology. Accordingly, stacking technology has been developed as another way of providing high capacity semiconductor products. According to the stacking technology, at least two semiconductor chips or semiconductor device packages are vertically stacked for providing high-capacity semiconductor products. For example, a 128-M memory chip can be fabricated by stacking two 64-M memory chips, and a 256-M memory chip can be fabricated by stacking two 128-M memory chips. In addition to the increase of storage capacity, semiconductor device packages can be mounted more densely and efficiently by using the stacking technology.
In general, a stack type (sometimes referred to as a “multi-chip”) semiconductor device package includes a first semiconductor device package and a second semiconductor device package. Connection terminals, such as a ball grid array (BGA), are disposed on a bottom surface of the first semiconductor device package for electrically connecting the first semiconductor device package to an external circuit, such as a circuit formed on a system substrate, and connection terminals, such as pads, are disposed on a top surface of the first semiconductor device package for electrically connecting the first semiconductor device package to the second semiconductor device package. In addition, connection terminals, such as pads, are also disposed on a bottom surface of the second semiconductor device package for electrically connecting the second semiconductor device package to the first semiconductor device package. Solder balls can be disposed between the connection terminals of the first and second semiconductor device packages for electrically connecting the first and second semiconductor device packages.
Electric characteristics, such as electrical connection states of the connection terminals of the first semiconductor device package, can be tested as follows. First, the electric characteristics of the connection terminals disposed on the bottom surface of the first semiconductor device package are tested using a test apparatus. Then, if it is determined that the electric characteristics of the connection terminals of the bottom surface of the first semiconductor device package are allowable, the electric characteristics of the connection terminals disposed on the top surface of the first semiconductor device package are tested. In detail, after connecting the second semiconductor device package to the first semiconductor device package using solder balls, the electric characteristics of the connection terminals of the top surface of the first semiconductor device package are tested by applying a signal to the second semiconductor device package through the connection terminals of the top surface of the first semiconductor device package and evaluating the operation state of the second semiconductor device package using the applied signal.
However, the above method takes a large amount of time to test all the connection terminals of the top and bottom surfaces of the first semiconductor device package.
Moreover, even if the second semiconductor device package is not defective, the second semiconductor device package can be discarded if it is determined that the electric characteristics of the connection terminals of the top surface of the first semiconductor device package are not allowable, i.e., defective.